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cy7c1350g 4-mbit (128 k 36) pipelined sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05524 rev. *l revised september 24, 2012 4-mbit (128 k 36) pipelined sram with nobl? architecture features pin compatible and functionally equivalent to zbt? devices internally self-timed output buffe r control to eliminate the need to use oe byte write capability 128 k 36 common i/o architecture 3.3 v power supply (v dd ) 2.5 v / 3.3 v i/o power supply (v ddq ) fast clock-to-output times ? 2.8 ns (for 200-mhz device) clock enable (cen ) pin to suspend operation synchronous self-timed writes asynchronous output enable (oe ) available in pb-free 100-pin tqfp package, pb-free and non pb-free 119-ball bga package burst capability ? linear or interleaved burst order ?zz? sleep mode option functional description the cy7c1350g is a 3.3 v, 128 k 36 synchronous-pipelined burst sram designed specifically to support unlimited true back-to-back read/write operatio ns without the insertion of wait states. the cy7c1350g is equipped with the advanced no bus latency? (nobl?) logic requir ed to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of the sram, especially in systems t hat require fre quent write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which, when deasserted, suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 2.8 ns (200-mhz device). write operations are controlled by the four byte write select (bw [a:d] ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate c ontrol. in order to avoid bus contention, the output drivers ar e synchronously tri-stated during the data portion of a write sequence. a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e clk cen write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s logic block diagram
cy7c1350g document number: 38-05524 rev. *l page 2 of 21 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 pin definitions .................................................................. 5 functional overview ........................................................ 6 single read accesses ................................................ 6 burst read accesses .................................................. 6 single write accesses ................................................. 6 burst write accesses .................................................. 6 sleep mode ................................................................. 6 interleaved burst address tabl e ................................. 7 linear burst address table ......................................... 7 zz mode electrical characteri stics .............................. 7 truth table ........................................................................ 8 partial truth table for read/write .................................. 9 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics ............................................... 10 capacitance .................................................................... 11 thermal resistance ........................................................ 11 ac test loads and waveforms ..................................... 11 switching characteristics .............................................. 12 switching waveforms .................................................... 13 ordering information ...................................................... 15 ordering code definitions ..... .................................... 15 package diagrams .......................................................... 16 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 document history page ................................................. 19 sales, solutions, and legal information ...................... 21 worldwide sales and design s upport ......... .............. 21 products .................................................................... 21 psoc solutions ......................................................... 21
cy7c1350g document number: 38-05524 rev. *l page 3 of 21 selection guide description 200 mhz 133 mhz unit maximum access time 2.8 4.0 ns maximum operating current 265 225 ma maximum cmos standby current 40 40 ma pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout a a a a a 1 a 0 nc/288m nc/144m v ss v dd nc/36m a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a adv/ld zz mode nc/72m nc/18m nc/9m cy7c1350g byte b byte a byte c byte d
cy7c1350g document number: 38-05524 rev. *l page 4 of 21 figure 2. 119-ball bga (14 22 2.4 mm) pinout pin configurations (continued) 23 4 56 7 1 a b c d e f g h j k l m n p r t u dq a v ddq nc/576m nc/1g dq c dq d dq c dq d aa aa nc/18m v ddq ce 2 a v ddq v ddq v ddq v ddq nc/144m nc a dq c dq c dq d dq d nc v dd a nc/72m dqp d a a adv/ld a ce 3 nc v dd aanc v ss v ss nc dqp b dq b dq b dq a dq b dq b dq a dq a nc nc nc v ddq nc v ss v ss v ss v ss v ss v ss v ss v ss mode ce 1 v ss oe v ss v ddq bw c nc/9m v ss we v ddq v dd v ss v dd v ss clk nc bw a cen v ss v ddq v ss zz nc/288m a a a1 a0 v ss v dd dqp c dq b a nc/36m dq c dq b dq c dq c dq c dq b dq b dq a dq a dq a dq a dqp a dq d dq d dq d dq d bw d bw b nc
cy7c1350g document number: 38-05524 rev. *l page 5 of 21 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the 128 k address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw [a:d] input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address co unter or load a new address. when high (and cen is asserted low) the inter nal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the directio n of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequenc e, during the first clock when emergi ng from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input plac es the device in a non-time critical ?sleep? condition with data integrity preserved. during normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in t he memory location specified by the address during the clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq s and dqp x are placed in a tristate condition. the outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emergi ng from a deselected state, and when the device is deselected, regardless of the state of oe . dqp [a:d] i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq s . during write sequences, dqp [a:d] is controlled by bw [a:d] correspondingly. mode input strap pin mode input. selects the burst order of the device . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . nc ? no connects . not internally connected to the die. 9m, 18m, 36m, 72m, 144m and 288m are address expansion pins in this device and will be used as address pins in their respective densities.
cy7c1350g document number: 38-05524 rev. *l page 6 of 21 functional overview the cy7c1350g is a synchronous-pipelined burst sram designed specifically to eliminat e wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.8 ns (200-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write oper ation, depending on the status of the write enable (we ). bw [a:d] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on- chip synchronous self-t imed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus, provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent oper ation (read/write/ deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will tristate following the next clock rise. burst read accesses the cy7c1350g has an on-chip bu rst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read accesses section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap around when incremented sufficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address inputs is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise t he data lines are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp [a:d] . in addition, the address for the subsequent access (read/write/deselect) is latch ed into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dqs and dqp [a:d] (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the wr ite operation is controlled by bw [a:d] signals. the cy7c1350g provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw [a:d] ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1350g is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp [a:d] inputs. doing so will tristate the output drivers. as a safety precaution, dqs and dqp [a:d] are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1350g has an on-chip bu rst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasse rting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write accesses section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw [a:d] inputs must be driven in each cycle of the burst wr ite in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low.
cy7c1350g document number: 38-05524 rev. *l page 7 of 21 interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz snooze mode standby current zz > v dd ?? 0.2 v ? 40 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to snooze current this parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit snooze curre nt this parameter is sampled 0 ? ns
cy7c1350g document number: 38-05524 rev. *l page 8 of 21 truth table the truth table for part cy7c1350g is as follows. [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l?h tristate continue deselect cycle none x l h x x x l l?h tristate read cycle (begin burst) external l l l h x l l l?h data out (q) read cycle (continue burst) n ext x l h x x l l l?h data out (q) nop/dummy read (begin burst) external l l l h x h l l?h tristate dummy read (continue burst) next x l h x x h l l?h tristate write cycle (begin burst) external l l l l l x l l?h data in (d) write cycle (continue burst) next x l h x l x l l?h data in (d) nop/write abort (begin burst) none l l l l h x l l?h tristate write abort (continue burst) next x l h x h x l l?h tristate ignore clock edge (stall) current x l x x x x h l?h ? snooze mode none xh x xxxx x tristate notes 1. x =?don't care.? h = logic high, l = logic low. ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by bw x , and we . see write cycle descriptions table. 3. when a write cycle is detected, all dqs are tri-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. cen = h, inserts wait states. 6. device will power-up deselected and the dqs in a tristate condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp [a:d] = tristate when oe is inactive or when the device is deselected, and dqs and dqp [a:d] = data when oe is active.
cy7c1350g document number: 38-05524 rev. *l page 9 of 21 partial truth table for read/write the partial truth table for read or wr ite for part cy7c1350g is as follows. [8, 9, 10] function we bw d bw c bw b bw a read h x x x x write ?? no bytes written l h h h h write byte a ??? (dq a and dqp a )lhhhl write byte b ??? (dq b and dqp b )lhhlh write bytes a, b l h h l l write byte c ?? (dq c and dqp c )lhlhh write bytes c, a l h l h l write bytes c, b l h l l h write bytes c, b, a l h l l l write byte d ??? (dq d and dqp d )llhhh write bytes d, a l l h h l write bytes d, b l l h l h write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes lllll notes 8. x =?don't care.? h = logic high, l = logic low. ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted , see write cycle description table for details. 9. write is defined by bw x , and we . see write cycle descriptions table. 10. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done on which byte write is active.
cy7c1350g document number: 38-05524 rev. *l page 10 of 21 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ????????????????????????????????????? 65 c to +150 c ambient temperature with power applied ????????????????????????????????????????????????? 55 c to +125 c supply voltage on v dd relative to gnd ??????? ? 0.5 v to +4.6 v supply voltage on v ddq relative to gnd ???????? 0.5 v to +v dd dc voltage applied to outputs in tristate ??????????????????????????????????????????????? ? 0.5 v to v ddq + 0.5 v dc input voltage ????????????????????????????????????? ? 0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch up current ..................................................... > 200 ma operating range range ambient temperature (t a ) v dd v ddq commercial 0 c to +70 c 3.3 v ? 5% / + 10% 2.5 v ? 5% to v dd industrial ? 40 c to +85 c electrical characteristics over the operating range parameter [11, 12] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage for 3.3 v i/o, i oh = ?? 4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?? 1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = ? 8.0 ma ? 0.4 v for 2.5 v i/o, i ol =1.0 ma ? 0.4 v v ih input high voltage [11] v ddq = 3.3 v 2.0 v dd + 0.3 v v v ddq = 2.5 v 1.7 v dd + 0.3 v v v il input low voltage [11] v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ? 55 ? a input current of mode input = v ss ? 30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ? 55 ? a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 5-ns cycle, 200 mhz ?265ma 7.5-ns cycle, 133 mhz ?225ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il f = f max = 1/t cyc 5-ns cycle, 200 mhz ?110ma 7.5-ns cycle, 133 mhz ?90ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 40 ma notes 11. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 12. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd.
cy7c1350g document number: 38-05524 rev. *l page 11 of 21 i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 5-ns cycle, 200 mhz ?95ma 7.5-ns cycle, 133 mhz ?75ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 45 ma electrical characteristics (continued) over the operating range parameter [11, 12] description test conditions min max unit capacitance parameter [13] description test conditions 100-pin tqfp max 119-ball bga max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v, v ddq = 3.3 v 55pf c clk clock input capacitance 5 5 pf c i/o input/output capacitance 5 7 pf thermal resistance parameter [13] description test conditions 100-pin tqfp package 119-ball bga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 30.32 34.1 c/w ? jc thermal resistance (junction to case) 6.85 14.0 c/w ac test loads and waveforms figure 3. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load note 13. tested initially and after any design or proc ess changes that may affect these parameters.
cy7c1350g document number: 38-05524 rev. *l page 12 of 21 switching characteristics over the operating range parameter [14, 15] description -200 -133 unit min max min max t power v dd (typical) to the first access [16] 1 ? 1 ? ms clock t cyc clock cycle time 5.0 ? 7.5 ? ns t ch clock high 2.0 ? 3.0 ? ns t cl clock low 2.0 ? 3.0 ? ns output times t co data output valid after clk rise ? 2.8 ? 4.0 ns t doh data output hold after clk rise 1.0 ? 1.5 ? ns t clz clock to low z [17, 18, 19] 0 ? 0 ? ns t chz clock to high z [17, 18, 19] ? 2.8 ? 4.0 ns t oev oe low to output valid ? 2.8 ? 4.0 ns t oelz oe low to output low z [17, 18, 19] 0 ? 0 ? ns t oehz oe high to output high z [17, 18, 19] ? 2.8 ? 4.0 ns setup times t as address setup before clk rise 1.2 ? 1.5 ? ns t als adv/ld setup before clk rise 1.2 ? 1.5 ? ns t wes gw , bw x setup before clk rise 1.2 ? 1.5 ? ns t cens cen setup before clk rise 1.2 ? 1.5 ? ns t ds data input setup before clk rise 1.2 ? 1.5 ? ns t ces chip enable setup before clk rise 1.2 ? 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? 0.5 ? ns t alh adv/ld hold after clk rise 0.5 ? 0.5 ? ns t weh gw , bw x hold after clk rise 0.5 ? 0.5 ? ns t cenh cen hold after clk rise 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? 0.5 ? ns notes 14. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 15. test conditions shown in (a) of figure 3 on page 11 unless otherwise noted. 16. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 17. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 3 on page 11 . transition is measured 200 mv from steady-state voltage. 18. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect paramete rs guaranteed over wo rst case user condi tions. device is designed to achieve tristate prior to low z under the same system conditions. 19. this parameter is sampled and not 100% tested.
cy7c1350g document number: 38-05524 rev. *l page 13 of 21 switching waveforms figure 4. read/write timing [20, 21, 22] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw [a:d] adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data in-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh don?t care undefined q(a6) q(a4+1) notes 20. for this waveform zz is tied low. 21. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 22. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal.
cy7c1350g document number: 38-05524 rev. *l page 14 of 21 figure 5. nop, stal l, and deselect cycles [23, 24, 25] figure 6. zz mode timing [26, 27] switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bw [a:d] adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 23. for this waveform zz is tied low. 24. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 25. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a write is not performed during this cycle. 26. device must be deselected when entering zz mode. see cycle descr iption table for all possible signal conditions to deselect the device. 27. dqs are in high z when exiting zz sleep mode.
cy7c1350g document number: 38-05524 rev. *l page 15 of 21 ordering code definitions ordering information the following table contains only the list of parts that are currently available. if yo u do not see what you are looking for, c ontact your local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code package diagram package type operating range 133 CY7C1350G-133AXC 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1350g-133axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free industrial cy7c1350g-133bgxc 51-85115 119-ball bga (14 22 2.4 mm) pb-free commercial 200 cy7c1350g-200axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1350g-200axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free industrial temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bg a = 100-pin tqfp; bg = 119-ball bga speed grade: xxx = 133 mhz or 200 mhz process technology: g ? 90 nm part identifier: 1350 = pl, 128 kb 36 (4 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1350 g - xxx x x cy 7 xx
cy7c1350g document number: 38-05524 rev. *l page 16 of 21 package diagrams figure 7. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1350g document number: 38-05524 rev. *l page 17 of 21 figure 8. 119-ball bga (14 22 2.4 mm) bg119 package outline, 51-85115 package diagrams 51-85115 *d
cy7c1350g document number: 38-05524 rev. *l page 18 of 21 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cen clock enable cmos complementary metal oxide semiconductor eia electronic industries alliance i/o input/output jedec joint electron devices engineering council nobl no bus latency oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt nm nanometer ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1350g document number: 38-05524 rev. *l page 19 of 21 document history page document title: cy7c1350g, 4-mbit (128 k 36) pipelined sram with nobl? architecture document number: 38-05524 rev. ecn no. issue date orig. of change description of change ** 224380 see ecn rkf new data sheet. *a 276690 see ecn vbl updated ordering information (changed tqfp package to pb-free tqfp package, added comment of bga pb-free package availability below the table). *b 332895 see ecn syt changed status from preliminary to final. updated features (removed 225 mhz and 100 mhz frequencies related information). updated selection guide (removed 225 mhz and 100 mhz frequencies related information). updated pin configurations (modified address expansion balls in the pinouts for 119-ball bga package as per jedec standards). updated electrical characteristics (updated test conditions for v ol and v oh parameters, removed 225 mhz and 100 mhz frequencies related information). updated thermal resistance (replaced tbd?s for ? ja and ? jc to their respective values). updated switching characteristics (removed 225 mhz and 100 mhz frequencies related information). updated ordering information (by removing shaded parts, changed the package name for 100-pin tqfp from a100ra to a101, removed comment on the availability of bga pb-free package). *c 351194 see ecn pci updated ordering information (updated part numbers). *d 419264 see ecn rxu changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (updated note 12 (changed test condition from v ddq < v dd to v ddq < v dd ), changed ?input load current except zz and mode? to ?input leakage current except zz and mode?). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). updated package diagrams . *e 419705 see ecn rxu updated features (added 100 mhz frequency related information). updated selection guide (added 100 mhz frequency related information). updated electrical characteristics (added 100 mhz frequency related information). updated switching characteristics (added 100 mhz frequency related information). *f 480368 see ecn vkn updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *g 2896584 03/20/2010 njy updated ordering information (removed obsolete part numbers). updated package diagrams . *h 3053085 10/08/2010 njy updated ordering information (updated part numbers) and added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *i 3211361 03/31/2011 cs updated ordering information (added cy7c1350g-133bgxc part number). *j 3353361 08/24/2011 prit updated functional description (updated note as ?for best practices recommendations, refer to sram system design guidelines .? and referred the note in same place in this section). updated package diagrams .
cy7c1350g document number: 38-05524 rev. *l page 20 of 21 *k 3590312 05/10/2012 njy / prit updated features (removed 250 mhz, 166 mhz and 100 mhz frequencies related information). updated functional description (removed the note ?for best practices recommendations, refer to sram system design guidelines .?). updated selection guide (removed 250 mhz, 166 mhz and 100 mhz frequencies related information). updated functional overview (removed 250 mhz, 166 mhz and 100 mhz frequencies related information). updated electrical characteristics (removed 250 mhz, 166 mhz and 100 mhz frequencies related information). updated switching characteristics (removed 250 mhz, 166 mhz and 100 mhz frequencies related information). *l 3753416 09/24/2012 prit updated package diagrams (spec 51-85115 (changed revision from *c to *d)). document history page (continued) document title: cy7c1350g, 4-mbit (128 k 36) pipelined sram with nobl? architecture document number: 38-05524 rev. ecn no. issue date orig. of change description of change
document number: 38-05524 rev. *l revised september 24, 2012 page 21 of 21 zbt is a trademark of integrated device technology, inc. nobl and no bus latency are trademarks of cypress semiconductor corpor ation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1350g ? cypress semiconductor corporation, 2006-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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